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Description: Hard-decision decoding scheme
Codeword length (n) : 31 symbols.
Message length (k) : 19 symbols.
Error correction capability (t) : 6 symbols
One symbol represents 5 bit.
Uses GF(2^5) with primitive polynomial p(x) = X^5 X^2 + 1
Generator polynomial, g(x) = a^15 a^21*X + a^6*X^2 + a^15*X^3 + a^25*X^4 + a^17*X^5 + a^18*X^6 + a^30*X^7 + a^20*X^8 + a^23*X^9 + a^27*X^10 + a^24*X^11 + X^12. Note: a = alpha, primitive element in GF(2^5) and a^i is root of g(x) for i = 19, 20, ..., 30.
Uses Verilog description with synthesizable RTL modelling.
Consists of 5 main blocks: SC (Syndrome Computation), KES (Key Equation Solver), CSEE (Chien Search and Error Evaluator), Controller and FIFO Register.
-Hard-decision decoding scheme Codeword l KV (n) : 31 symbols. Message length (k) : 19 symbols. Error correction capability (t) : 6 symbols One symbol represents five bit. Uses GF (2 ^ 5) with primitive polynomial p (x) = x ^ x ^ 5 2 1 Ge nerator polynomial. g (x) = a ^ a ^ 15 * 21 ^ 6 a X * X ^ a ^ 15 2 * X ^ a ^ 3 25 * X ^ a ^ 4 17 5 * X ^ a ^ 18 ^ 6 X * a * X 30 ^ 7 ^ a ^ 20 * X ^ a ^ 23 8 * X ^ a ^ 9 * 27 X 10 ^ a ^ 24 * 11 ^ X ^ X 12. Note : a = alpha, primitive element in GF (2 ^ 5) and a ^ i is the root of g (x) for i = 19, 20, ..., 30. Uses Verilog description with synthesizab le RTL modeling. Consists of five main blocks : SC (Syndrome Computation), KES (Key Equation Solver). CSEE (Chien Search and Error Evaluator) Controller and FIFO Register.
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Size: 14247 |
Author: 孟轲敏 |
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Description: 基于FPGA的异步FIFO的软硬件实现,通过VERILOG编程实现后下载到FPGA芯片
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Author: youren |
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Description: 同步FIFO功能，verilog语言描述，通过了modelsim 6.0 仿真，Quartue综合
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Size: 26159 |
Author: shenyunfei |
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Description: 一种新的FIFO实现方法,verilog描述，通过modelsim 6.0 仿真，Quartue综合
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Size: 2793 |
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Description: verilog语言编写可综合FIFO。简单实用
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Author: 苗苗 |
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Description: 一个可综合的同步FIFO的verilog源代码
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Size: 2754 |
Author: 李东临 |
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Description: 一个verilog语言描写的同步fifo,包括:Fifo using declared registers for storage和Fifo using (model of) standard memory chip for storage.两种方式,包含testbench
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Size: 2279 |
Author: 彭帅 |
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Description: 设计FIFO,使用VERILOG的一篇文章
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Size: 119762 |
Author: 丁过州 |
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Description: 自己编写的串口UART发送的Verilog模块。与FIFO连接，可以实现自动连续发送。
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Size: 7321 |
Author: YongZhiLi |
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Description: 异步fifo的verilog程序，含有测试平台
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Size: 2819 |
Author: dq |
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Description: Generic FIFO, writen in verilog hdl
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Size: 12782 |
Author: marco |
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Description: FIFO的部分verilog代码，其余部分我会陆续上传，
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Size: 136854 |
Author: 常勇 |
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Description: verilog fifo
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Size: 4311 |
Author: 王新 |
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Description: 一个可以综合的Verilog 写的FIFO存储器，word格式
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Size: 19723 |
Author: hjx |
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Description: UART16550兼容的串行通讯控制器，Verilog语言描述，采用Altera Cyclone系列芯片实现FPGA综合，因为FIFO部分利用到内部资源实现。已经在某项目中成功应用，特此推出。
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Size: 10619 |
Author: David.Mr.Liu |
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Description: FIFO电路Verilog实现
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Size: 3618 |
Author: Jerry |
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Description: 基于Verilog HDL的异步FIFO设计与实现
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Description: 《Verilog HDL 语言编程》
异步FIFO设计（基于Verilog)
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Description: 一个异步FIFO的verilog实现论文
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Size: 262486 |
Author: Roger |
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Description: 用Verilog语言编写的实现NAND Flash块的控制存取以及同步的FIFO的控制
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Size: 6481 |
Author: 刘义春 |
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